1. Field of the Invention
The present invention relates to computer systems and, more particularly, to transmission of interrupts within a computer system.
2. Description of the Related Art
A primary component of most computer systems (e.g., Apple Macintosh computers and IBM compatible computers) is a microprocessor. The microprocessor controls the operations of the computer system and interacts with other supporting devices or integrated circuit chips. One such supporting integrated circuit chip is known as an interrupt controller. An interrupt controller receives interrupt signals from a variety of peripherals or special purpose devices of or associated with the computer system. Examples of the peripherals or special purpose devices include: direct-memory-access (DMA) controllers, Ethernet boards or controllers, removable cards or storage devices (e.g., PC-CARDs, PCMCIA, data storage drives, etc.). The interrupt controller manages the various interrupt signals and then informs the microprocessor that an interrupt is needed to service one or more of the peripherals or special purpose devices.
FIG. 1 is a block diagram of a portion 100 of a conventional computer system. The portion 100 includes a microprocessor 102 and an interrupt controller 104. The interrupt controller 104 receives a plurality of interrupt signals 106, performs interrupt management processing, and then outputs a main interrupt signal 108 to the microprocessor 102.
In more recent computer system designs, interrupt controllers have become integrated within other supporting chips of a computer system. In one case, the supporting chip that cooperates with the interrupt controller is an input/output (I/O) controller of the computer system. The I/O controller manages the control of input and output operations to and from the computer system. Even though the interrupt controller is integrated within an I/O controller, the general functioning of the interrupt controller is the same as it was when the interrupt controller was a separate integrated circuit chip. Interrupt controllers have also been incorporated within supporting chips of the computer system other than the I/O controller.
FIG. 2 is a block diagram of a portion 200 of another conventional computer system. The portion 200 of the computer system illustrated in FIG. 2 includes an I/O controller 202, a memory controller 204, and a microprocessor 206. The memory controller 204 includes an interrupt controller 208. In other words, the integrated circuit chip housing the memory controller 204 also houses the interrupt controller 208. The various interrupt signals that the I/O controller 202 receives from the various peripheral and special purpose devices are forwarded to the interrupt controller 208 within the memory controller 204 via a plurality of links 210. The links 210 are preferably wires (e.g., metal traces on a circuit board) and each of the wires corresponds to one of the incoming interrupt signals received (or generated) by the I/O controller 202. Upon receiving the interrupt signals over the links 210, the interrupt controller 208 performs interrupt management processing and outputs a main interrupt signal 212 to the microprocessor 206.
The portion 200 of the computer system illustrated in FIG. 2 has a number of disadvantages. One disadvantage is that the number of links 210 connecting the I/O controller 202 to the memory controller 204 is large and onerous. In particular, one link 210 is required for each interrupt signal being supported by the computer system. For example, currently most Apple Macintosh computers being produced support at least 20-30 different interrupt signals. Thus, for the portion 200 of the computer system design illustrated in FIG. 2, at least 20-30 separate links 210 would be required. Another disadvantage is that both the I/O controller 202 and the memory controller 204 are required to have pins for each of the links 210 that are required.
One recent attempt to overcome the problems of the need for a substantial amount of wiring (links) and pins is documented in "Serialized IRQ Support for PCI Systems," Version 6.0, Sep. 1, 1995, by Compaq Computer Corporation, Cirrus Logic Inc., National Semiconductor Corporation, OPTi Inc., Standard Microsystems Corporation, Texas Instruments Inc., and VLSI Technology Inc. This approach operates to transmit interrupt signals serially from an I/O controller to an interrupt controller. While this approach is successful in reducing the number of links (wires) and pins required, it is disadvantageous in that a large latency can nevertheless be induced. More particularly, given that the forwarding of the interrupt signals by the I/O controller is done with a sequential processing, the reception of the interrupt signals at the interrupt controller is also performed with a sequential processing. As a consequence, this recent design is susceptible to large latencies which are undesirable in processing interrupt requests. Another disadvantage of this recent approach is that there is no support for edge triggered interrupt sources.
Thus, there is a need for an improved method and apparatus for managing interrupt requests from various sources with reduced latency and without requiring a large number or quantity of wires or pins.